In wafer fabricating processes, a damascene technique in combination with CMP has been employed for patterning Cu interconnect structures. After Cu lines are formed, the remaining metal on top of the patterns is removed using CMP, which is generally safe for the surface of metal patterns, interlevel dielectrics (ILD)/barrier interfaces, and barrier/metal interfaces. However, under certain conditions during the metal CMP process, for example, during drift over pad lifetime, the metal surface may be subjected to chemical activity that may result in defects negatively effecting the reliability of the Cu lines. Such defects include side-wall corrosion and voids in the metal surface, as well as Cu residue remaining on the surface. To find and discard defective wafers, and to prevent production of additional defective wafers, it is necessary to incorporate testing of the wafer surfaces, particularly Cu pattern surfaces, into the process. The standard defect-analysis scan tests only a small percentage of wafers, for example only a few wafers in every fifth or sixth lot are scanned (where a lot includes 25 wafers). This system is characterized by a high delay time for defect inspection feedback. Therefore, a large number of wafers may become defective before any defects are realized and the occurrence of defects in subsequently fabricated wafers may be prevented.
A need therefore exists for methodology enabling testing of every wafer, without additional processing time, and preventing production of further defective wafers.